Intel, IBM developing mobile phone processors

Intel Corp. and IBM Corp. this week disclosed details of their new 22-nanometer manufacturing technologies aimed squarely at mobile devices, capping the International Electron Devices Meeting (IEDM) in San Francisco.

 

While IBM said it is prototyping server processors in a 3-D ready technology, Intel disclosed a variant of its 22-nm process for systems on a chip (SoC's) such as smartphones.

 

According to a report on EE Times, Intel's paper showed support for “high drive current across the spectrum of leakage and a full suite of SoC tools,” which Mark Bohr, head of Intel’s process technology development group, said is designed for a much larger array of designs than that of IBM.

 

Bohr said Intel’s 22-nm FinFET process is cost-effective, and adds only three percent to the cost of the process.

 

“Cost per wafer has always gone up marginally each generation, somewhat more so in recent generations, but that’s more than offset by increases in transistor density so that the cost per transistor continues to go down at 14 nm,” Bohr said.

 

Intel's paper cited figures indicating the 22-nm process variation for SoCs can outperform its 32-nm planar process by 20 to 65 percent.

 

The process provides 51 to 56 percent improvements in high voltage performance used for interfaces such Ethernet, HDMI and PCI Express, it said.

 

Analog performance also went up three-fold after declines in the past three nodes.

 

Intel created two new transistor designs specifically for the 22-nm SoC variant. One focuses on low power and the other on high voltage for mixed-signal and analog circuits.

 

IBM's design

 

Meanwhile, IBM researcher S. Narasimha said IBM's 22-nm process uses partially depleted silicon-on-insulator, with IBM having prototyped "a number of server processors” in the node that achieve latency below 1.5 ns and 750 MHz random clock cycles.

 

While Narasimha declined to give specifics of what IBM might achieve with the 22-nm node, he said the goal was to provide 25 to 35 percent boosts of the previous node, which delivered server processors running up to 5.5 GHz and others with up to 80 Mbytes embedded DRAM.

 

EE Times said IBM had created an SRAM cell that measures 0.026 mm2 using the process. It also power supplies at 1.2V across a 550 mm2 die area, Narasimha said. —TJD, GMA News